1. Field of the Invention
The present invention relates to a semiconductor device testing technique. Particularly, the present invention relates to a semiconductor test unit for use in a reliability test and the like for a semiconductor device such as a burn-in, a contact board for a semiconductor device test, a method of testing a semiconductor device, and a method of manufacturing the same.
2. Description of the Related Art
Semiconductor devices must be tested for their product lives at their trial stages or after being manufactured as actual products in development processes and mass production processes. In general, reliable tests are performed while placing the semiconductor devices under various environments. In a general semiconductor testing process, an electrical characteristic test is conducted on a semiconductor wafer in which electric circuits compose of semiconductor elements and the like are formed, thereby screening semiconductor chips into good and defective ones. Next, the wafer is divided into each chip by dicing, and then the chips are assembled into packaged states. Furthermore, the packages are screened into good and defective ones by an electrical characteristic test. Next, a burn-in test (high temperature bias test) is conducted to perform reliability screening. The burn-in test is conducted at one hundred and tens of degrees Celsius for tens of hours to one hundred and tens of hours in order to screen out initial failures including the gate oxide film breakdown of transistors and the breakage or short circuit of wirings of semiconductor elements. After the burn-in test, an electrical characteristic test is conducted as the final test. As a conventional reliability test of semiconductor devices, a test requiring a long time for assembling semiconductor chips into a package has been known. In a general semiconductor test process, the costs for assembling chips having no reliability problems are a problem. Particularly, in the case where many chips are mounted in one package such as a multi chip module (MCM) or where a bare die for COB (Chip On Board) must be supplied, the KGD (Known Good Die) technology is necessary, and it is preferable to conduct a burn-in test before an assembly process.
On the other hand, it is also possible to conduct a chip level burn-in test by accommodating each diced chip in a temporal package. However, a chip level burn-in test has a problem that costs, the number of steps, and processing time increase because of the adoption of the KGD technology. Therefore, a wafer level burn-in test has been proposed. As described in Japanese Unexamined Patent Publication No. Hei 10(1998)-284556 and the like, in a wafer level burn-in test, on a support a wafer is held with an element forming surface facing upward, where electrodes are formed, and the following burn-in system is used. The burn-in system has a multilayer sheet having protruding electrodes at the positions facing the electrodes provided on the wafer, a conductive soft member at the positions facing the electrodes, a burn-in base substrate unit showing high flatness, in which a test circuit are formed, and a mechanism for applying pressure.
In the conventional semiconductor test unit as described above, there are the following problems. In the wafer level burn-in test, high pressure needs to be applied because of variations in the heights of electrode bumps provided on the wafer. In the case of a thin wafer, a load is locally applied to the wafer, and there is a risk that the wafer may be cracked or broken when high pressure is applied thereto. In addition, though a multilayer sheet is provided with conductive portions, as electrodes having lengths of 50 μm with a fine pitch of 100 μm so as to correspond to the electrodes, there may be a case where a sufficient contact area cannot be obtained when the pitch between the electrodes is narrowed and the electrode size is reduced. Particularly, if the electrodes of the wafer, which is an examined electronic product, have inequalities in height, or if the wafer is warped by its weight, a stable test result cannot be obtained. This is because the contact areas to the electrodes of a test board largely differ depending on the electrodes of the wafer even if the wafer is pressed to the test board with strong pressure. In the conventional burn-in system, in order to allow all electrodes on the wafer to simultaneously contact with the electrodes of the test board, application of a local load to the wafer must be avoided. In other words, high flatness is strictly required for the substrate unit. Furthermore, in order to ease the position deviation among electrodes and mechanical stresses due to the difference between the thermal expansion coefficient of the base unit and that of the wafer, two components, which are a multilayer sheet and a member, are necessary. Since the components, i.e. the multilayer sheet and the member, are basically expendables, the cost for members increases.